Today's communication market faces strong competition and multiple new standards. For this reason, many systems, such as mobile devices, networking products, and modems require new embedded processors (EP). These EPs can either be general purpose, such as microcontrollers (μC) and digital signal processors (DSP), or application specific, using application specific instruction set processors (ASIP). Finding a best-in-class solution involves exploring the tradeoff between a general design that is highly flexible and a specific design that is highly optimized. This design exploration phase is conventionally very time consuming; however, given the importance of short product development cycle times, reducing the time required for the design exploration phase is highly significant.
Moreover, the design exploration phase is only a portion of the overall development process. The development process of new EPs is separated into several development phases, such as design exploration, software tools design, system integration, and design implementation. Significantly, the different design phases are assigned to different design engineering groups with specific expertise in their respective fields. Moreover, software tools and description languages vary from phase to phase. Thus, another important factor in the design of a new architecture is communication and verification between different design groups or at least design phases.
Another obstacle in the development process is that design tools that are used in one phase are often not suitable for use in another phase. Two types of languages that are used in the development process are hardware description languages (HDL) and instruction set languages (ISL). Hardware description languages (HDLs), such as VHDL or Verilog, are widely used to model and simulate processors, but mainly with the goal of implementing hardware. However, there are a number of drawbacks in using HDL models to explore the new architecture and to generate production quality software development tools, especially for cycle-based or instruction-level processor simulation. One disadvantage is that HDLs cover a huge amount of hardware implementation details that are not needed for performance evaluation, cycle-based simulation, and software verification. On the other hand, ISLs are mainly designed to retarget the software development tools, sometimes a complete tool suite. However, ISLs operate on a high level of abstraction to provide as much convenience as possible for fast and efficient design exploration phases. Unfortunately, ISLs do not contain the required information about the underlying hardware to allow a hardware description to be formed therefrom. Conventional development processes that use an ISL and an HDL require that new code be written in each language each time a modification is made to the design of the architecture being developed.
Therefore, it would be advantageous to provide a method that reduces the time required for the design exploration phase when designing a new processor. It would be further advantageous to provide such a method that facilitates communication and verification between different design groups and phases in the development process. It would be further advantageous to meet the above constraints while being compatible with existing technologies for developing processors.